Interrupts and exceptions are special kinds of control transfer; they alter the normal program flow to handle external events or to report errors or exceptional conditions.
The difference between interrupts and exceptions is that interrupts are used to handle events external to the processor, but exceptions handle conditions detected by the processor itself while executing instructions (like divide by 0, invalid opcode, floating point exception etc).
Identifying an interrupt/exception
Intel processor associates an identifying number (ranging from 0 to 255) with each different type of interrupt or exception. Intel calls this identifying number a vector.
Intel processor associates an identifying number (ranging from 0 to 255) with each different type of interrupt or exception. Intel calls this identifying number a vector.
Interrupt and Exception numbers on x86 processors
Vector Number Description
0 Divide by Zero
1 Debug exceptions
2 Nonmaskable interrupt
3 Breakpoint (one-byte INT 3 instruction)
4 Overflow (INTO instruction)
5 Bounds check (BOUND instruction)
6 Invalid opcode
7 Coprocessor not available
8 Double fault
9 Reserved
10 Invalid TSS
11 Segment not present
12 Stack exception
13 General protection
14 Page fault
15 Reserved
16 Coprocessor error
17-31 Reserved
32-255 Available for external interrupts via
INTR pin
The vectors of nonmaskable interrupt and exceptions are fixed.
IRQs and external interrupts
The external devices like scsi disks, sound cards, network cards etc may be assigned any vector in the range 32 – 228.
IRQs and external interrupts
The external devices like scsi disks, sound cards, network cards etc may be assigned any vector in the range 32 – 228.
Linux uses vector 28 (0x80) to implement system calls.
The IBM compatible PC architecture requires that some devices should be allocated particular fixed vector number as shown in following table.
IRQ | INT | Hardware device |
0 | 32 | Timer |
1 | 33 | Keyboard |
2 | 34 | PIC cascading |
3 | 35 | Second serial port |
4 | 36 | First serial port |
6 | 38 | Floppy disk |
8 | 40 | System clock |
10 | 42 | Network card |
11 | 43 | USB port, sound card |
12 | 44 | PS/2 mouse |
13 | 45 | Mathematical coprocessor |
14 | 46 | EIDE disk controller's first chain |
15 | 47 | EIDE disk controller's second chain |
Interrupt vectors as used by Linux on an x86 processor
Vector Range | Use |
0 – 16 | Nonmaskable interrupts and exceptions |
17 - 31 | Intel-reserved |
32 - 127 | Maskable External interrupts (IRQs) |
128 (0x80) | Software interrupt for system calls (int 0x80) |
129 - 238 | External interrupts (IRQs) |
239 | Local APIC timer interrupt |
240 | Local APIC thermal interrupt |
241 - 250 | Reserved by Linux for future use |
251 – 253 | Interprocessor interrupts |
254 (0xfe) | Local APIC error interrupt (generated when the local APIC detects an erroneous condition) |
255 (0xff) | Local APIC spurious interrupt (generated if the CPU masks an interrupt while the hardware device raises it) |
Enabling and Disabling Interrupts on intel x86 processor
The external interrupts that are signaled via the INTR pin of the processor can be enabled/disabled by the IF bit of flag register.
When IF=0, INTR interrupts are inhibited.
When IF=1, INTR interrupts are enabled.
The instructions CLI and STI alter the setting of IF.
CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register).
These instructions may be executed only by the linux kernel code that runs at a higher privilege level as compared to the user program. The user process cannot enable/disable the interrupts.
Programmable Interrupt Controller (PIC 82596)Each hardware device (like keyboard, sound card, hard disk etc) capable of issuing an interrupt request has an output line known as IRQ line. These IRQ lines are connected to the input pins of programmable interrupt controller (PIC 82596).
So, IRQ0 is associated with vector number 32.
IRQN is associated with vector number 32 + N
Each IRQ can be selectively disabled. The PIC can be programmed to disable IRQ. The disabled interrupts are not lost and are issued to the CPU as soon as they are enabled again.
Typically on a PC, the PICs are implemented by connecting them in cascade as shown in figure above. Each 82596 chip can handle up to 8 IRQ input lines.
The INT output of slave PIC is connected to the IRQ 2 of the master PIC as is used for cascading. So, only 15 IRQ lines are available to the external devices.
The 8 IRQ lines are first passed through the IMR (Interrupt Mask Register) to see if they are masked or not. If a particular interrupt is masked then it is not processed further. If it is not masked it will register its request with the Interrupt Request Register (IRR) by setting the corresponding bit in it. The priority resolver then selects the highest priority interrupt and set the corresponding bit in the ISR register.
Sequence of events in handling an interrupt request
1) One or more IRQ lines (IRQ0 to IRQ15) are raised high by the external device connected to these lines. This results in setting the corresponding bits in IRR (Interrupt Request Register).
2) The chip 82596 sends INT to CPU (ie INT line on the processor is asserted)
3) CPU acknowledges the INT and responds with INTA pulse
4) Upon receiving INTA from CPU, the highest priority bit from IRR is selected and the corresponding bit in ISR (Interrupt Service Register) is set. The selected bit in IRR is reset.
1) One or more IRQ lines (IRQ0 to IRQ15) are raised high by the external device connected to these lines. This results in setting the corresponding bits in IRR (Interrupt Request Register).
2) The chip 82596 sends INT to CPU (ie INT line on the processor is asserted)
3) CPU acknowledges the INT and responds with INTA pulse
4) Upon receiving INTA from CPU, the highest priority bit from IRR is selected and the corresponding bit in ISR (Interrupt Service Register) is set. The selected bit in IRR is reset.
The ISR bit shows which IRQ is being currently served.
The corresponding bit in IRR is reset as it is no longer requesting service but actually getting service.
5) CPU then initiates a second INTA pulse to tell the PIC to place the 8 bit IRQ number on the the data bus (corresponding the vector number of IRQ being serviced).
6) CPU then reads the data bus to find out the interrupt vector number to call the associated Interrupt handler code.
7) Once the interrupt handler (ISR) is done, it sends an EOI (End of Interrupt) to the PIC. The PIC will then determine the next highest priority interrupt and repeat the same process.
This is all for today. In the next article we will see how interrupts are handled by linux kernel and discuss in more details about them.
5) CPU then initiates a second INTA pulse to tell the PIC to place the 8 bit IRQ number on the the data bus (corresponding the vector number of IRQ being serviced).
6) CPU then reads the data bus to find out the interrupt vector number to call the associated Interrupt handler code.
7) Once the interrupt handler (ISR) is done, it sends an EOI (End of Interrupt) to the PIC. The PIC will then determine the next highest priority interrupt and repeat the same process.
This is all for today. In the next article we will see how interrupts are handled by linux kernel and discuss in more details about them.
Till then, Have Fun !!!
